{"id":693,"date":"2026-10-16T19:53:39","date_gmt":"2026-10-16T19:53:39","guid":{"rendered":"https:\/\/glassubstrate.net\/en\/?p=693"},"modified":"2026-10-22T01:23:41","modified_gmt":"2026-10-22T01:23:41","slug":"glass-wafer-bonding-guide","status":"publish","type":"post","link":"https:\/\/glassubstrate.net\/ru\/glass-wafer-bonding-guide\/","title":{"rendered":"Glass Wafer Bonding: Materials, Methods and an RFQ Checklist"},"content":{"rendered":"

Glass wafer bonding starts before the wafers enter a bonding tool. The glass composition, thickness uniformity, surface condition and edge quality determine which bonding route can be evaluated and whether the pair can be aligned, contacted and inspected reliably. A \u201cbond-ready glass wafer\u201d is therefore a specification agreed for a particular stack and process\u2014not a universal grade of glass.<\/p>\n

This guide is for engineers and buyers sourcing glass wafers for MEMS caps, optical packages, carrier wafers and other wafer-level assemblies. It compares common bonding routes, then turns the intended process into a practical glass-wafer RFQ.<\/p>\n

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Scope:<\/strong> The method descriptions below are selection guidance, not guaranteed recipes. Bonding temperature, voltage, pressure, atmosphere, strength and hermeticity must be qualified for the actual glass, mating wafer, equipment and device design.<\/p>\n<\/div>\n

What does the glass wafer do in the bonded stack?<\/h2>\n

A glass wafer may be a transparent cap over a sensor, a structured lid with cavities or feedthroughs, an electrically insulating substrate, or a temporary carrier for handling a thin device wafer. These roles impose different requirements. A cap may need a defined optical window and seal path; a carrier may need a release method; a structured wafer needs geometry that survives cleaning and bonding.<\/p>\n

Define the function and the mating material first. A silicon-to-glass MEMS cap is not the same procurement problem as glass-to-glass microfluidics or a temporarily bonded glass carrier. The bonding route follows the interface, thermal budget and required seal\u2014not the product name alone.<\/p>\n

Which bonding method fits the glass wafer?<\/h2>\n
\n\n\n\n\n\n\n\n\n
Bonding route<\/th>\nTypical interface and principle<\/th>\nWhat to establish before buying the glass<\/th>\n<\/tr>\n<\/thead>\n
Anodic bonding<\/strong><\/td>\nUsually silicon to a compatible, mobile-ion-containing glass; heat and an electric field promote the interfacial bond without an added adhesive.<\/td>\nConfirm the exact glass grade, thermal-expansion behavior, exposed bonding surface, silicon stack, cleanliness and bond-tool window. Do not assume any transparent or alkali-free glass will anodically bond.<\/td>\n<\/tr>\n
Direct \/ fusion bonding<\/strong><\/td>\nPrepared surfaces are brought into intimate contact without a separate bonding layer; surface activation and subsequent treatment depend on the material pair.<\/td>\nAgree on surface preparation, roughness, topography, particles, coatings and allowable thermal budget with the bonding partner. One fixed annealing temperature is not valid for every stack.<\/td>\n<\/tr>\n
Adhesive bonding<\/strong><\/td>\nAn organic bonding layer connects the wafers; the adhesive and cure route are chosen for the application.<\/td>\nSpecify allowable bond-line thickness, outgassing, chemical exposure, optical path and whether the assembly needs a qualified hermetic seal. An adhesive joint is not automatically hermetic.<\/td>\n<\/tr>\n
Glass-frit or metal-based bonding<\/strong><\/td>\nA patterned intermediate seal or metal interface forms the joint.<\/td>\nDefine the seal-ring geometry, deposited materials, topography, alignment, electrical features and thermal compatibility. These are stack-level processes, not properties of a bare glass blank.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n

Equipment maker EV Group lists adhesive, anodic, direct\/fusion, glass-frit and metal-based processes as distinct routes. Its anodic-bonding guidance specifically calls for a suitable alkali-containing borosilicate glass and clean, contacting wafer surfaces. The final route should be selected with the team that will perform the bonding. See EV Group’s anodic-bonding overview.<\/p>\n

Choose the glass material for the interface<\/h2>\n

BOROFLOAT\u00ae 33<\/a> and SCHOTT MEMpax\u00ae are examples of borosilicate materials used in silicon\u2013glass anodic-bonding applications. SCHOTT describes MEMpax\u00ae as having thermal expansion compatible with silicon and a very smooth as-drawn surface. These are manufacturer material characteristics, not a guarantee that every wafer format or finished part will meet a particular bonding yield.<\/p>\n

Fused silica<\/a> can be attractive where the optical wavelength, chemical environment or low thermal expansion drives material choice. Its suitability for a particular bonding method must still be checked against the mating wafer and process. Likewise, selecting an alkali-free display glass for low mobile-ion content does not by itself make it a substitute for a glass specified for anodic bonding.<\/p>\n

For an optical cap, request transmission data at the actual operating wavelength and representative thickness, including any coatings. A generic spectrum of a different thickness is not a wafer-bonding acceptance criterion. For a non-optical cap or carrier, geometry, surface and cleanliness may be more important than a transmission graph.<\/p>\n

Specify the wafer\u2014not just the glass name<\/h2>\n

The same material can be supplied in different wafer geometries and surface conditions. Before asking for a price, separate material properties from finished-wafer acceptance criteria:<\/p>\n

\n\n\n\n\n\n\n\n\n\n\n
RFQ item<\/th>\nWhat to define<\/th>\nWhy it matters<\/th>\n<\/tr>\n<\/thead>\n
Material and lot<\/td>\nManufacturer\/grade, certificate or traceability requirement, mating wafer and intended bonding route.<\/td>\nComposition and thermal behavior affect process compatibility.<\/td>\n<\/tr>\n
Format<\/td>\nDiameter or panel size, nominal thickness and tolerance, flat\/notch, orientation and handling requirements.<\/td>\nTooling, alignment and downstream dicing depend on the format.<\/td>\n<\/tr>\n
Geometry<\/td>\nTotal thickness variation (TTV), bow\/warp, flatness and the measurement area and support condition.<\/td>\nThese describe different aspects of a wafer; one number does not replace the others.<\/td>\n<\/tr>\n
Bonding face<\/td>\nWhich face bonds, polishing state, roughness parameter and measurement method, scratches, pits and allowable edge exclusion.<\/td>\nContact quality depends on the actual interface, not an unspecified \u201coptical-grade\u201d label.<\/td>\n<\/tr>\n
Structures and edges<\/td>\nCavities, through-holes, alignment marks, seal-ring land, bevel and chipping limits.<\/td>\nFeatures and edge damage can interfere with sealing, alignment or cleaning.<\/td>\n<\/tr>\n
Cleanliness and packing<\/td>\nParticle\/organic-residue criteria, final clean, inspection, packaging and shelf-life or re-clean requirements.<\/td>\nContamination introduced after polishing can prevent intimate contact.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n

SEMI’s guidance treats thickness, TTV, bow, warp and flatness as separate parameters that affect bonded-wafer processing. Avoid importing a competitor’s headline TTV or roughness value into your drawing without specifying wafer size, thickness, measurement conditions and the actual bonding application.<\/p>\n

\"Operator
Glass-wafer dimensions and edges should be checked against the drawing before bond-surface preparation. Photo: LIGHTING.<\/figcaption><\/figure>\n

From glass blank to a bond-ready component<\/h2>\n
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  1. Confirm the stack and process.<\/strong> Identify the mating wafer, interface materials, working temperature limit, electrical or optical function, and whether the bond is temporary or permanent.<\/li>\n
  2. Form the wafer.<\/strong> Cut or shape to the required outline, then prepare the flat\/notch and edge profile. Define edge chips and handling zones on the drawing.<\/li>\n
  3. Prepare the functional faces.<\/strong> Grind or polish only to the surface and geometry specification required by the selected route. If cavities, vias or marks are needed, plan their sequence relative to finishing and coatings.<\/li>\n
  4. Clean, inspect and protect.<\/strong> Inspect geometry and visible defects using agreed methods. Specify final cleaning and packaging so a qualified surface does not arrive contaminated.<\/li>\n
  5. Qualify the assembly.<\/strong> The bonding team validates alignment, voids, strength, hermeticity and post-bond geometry on the real stack. A passed incoming-glass inspection does not replace bonded-device qualification.<\/li>\n<\/ol>\n
    \"Thin
    Handling and separation during processing matter for thin glass wafers; the photograph shows glass wafers, not a completed bonded stack. Photo: LIGHTING.<\/figcaption><\/figure>\n

    A concise glass-wafer RFQ checklist<\/h2>\n

    To request a useful quotation for custom glass wafers<\/strong>, borosilicate glass wafers for anodic bonding<\/strong> or precision glass wafer processing<\/strong>, send the drawing and answer these questions:<\/p>\n